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| 80C186XL 80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power Fully Static Versions of 80C186 80C188 Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 (80C186XL Only) Compatible Mode NMOS 80186 80188 Pin-for-Pin Replacement for Non-Numerics Applications Integrated Feature Set Static Modular CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-Bit Timers Dynamic RAM Refresh Control Unit Programmable Memory and Peripheral Chip Select Logic Programmable Wait State Generator Local Bus Controller Power-Save Mode System-Level Testing Support (High Impedance Test Mode) Y Y Completely Object Code Compatible with Existing 8086 8088 Software and Has 10 Additional Instructions over 8086 8088 Speed Versions Available 25 MHz (80C186XL25 80C188XL25) 20 MHz (80C186XL20 80C188XL20) 12 MHz (80C186XL12 80C188XL12) Direct Addressing Capability to 1 MByte Memory and 64 Kbyte I O Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) Ceramic Pin Grid Array (PGA) Ceramic Leadless Chip Carrier (JEDEC A Package) Available in 80-Pin Quad Flat Pack (EIAJ) Shrink Quad Flat Pack (SGFP) Available in Extended Temperature Range ( b 40 C to a 85 C) Y Y Y Y Y Y The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor It offers higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional compatibility Packaging and pinout are also identical 272431-1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 COPYRIGHT INTEL CORPORATION 1995 Order Number 272431-004 1 80C186XL 80C188XL 16-Bit High-Integration Embedded Processors CONTENTS INTRODUCTION 80C186XL CORE ARCHITECTURE 80C186XL Clock Generator Bus Interface Unit 80C186XL PERIPHERAL ARCHITECTURE Chip-Select Ready Generation Logic DMA Unit Timer Counter Unit Interrupt Control Unit Enhanced Mode Operation Queue-Status Mode DRAM Refresh Control Unit Power-Save Control Interface for 80C187 Math Coprocessor (80C186XL Only) ONCE Test Mode PACKAGE INFORMATION Pin Descriptions 80C186XL 80C188XL Pinout Diagrams ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC SPECIFICATIONS Power Supply Current PAGE 4 4 4 5 5 5 6 6 6 6 6 7 7 7 7 8 8 16 22 22 22 23 CONTENTS AC SPECIFICATIONS Major Cycle Timings (Read Cycle) Major Cycle Timings (Write Cycle) Major Cycle Timings (Interrupt Acknowledge Cycle) Software Halt Cycle Timings Clock Timings Ready Peripheral and Queue Status Timings Reset and Hold HLDA Timings AC TIMING WAVEFORMS AC CHARACTERISTICS EXPLANATION OF THE AC SYMBOLS DERATING CURVES 80C186XL 80C188XL EXPRESS 80C186XL 80C188XL EXECUTION TIMINGS INSTRUCTION SET SUMMARY REVISION HISTORY ERRATA PRODUCT IDENTIFICATION PAGE 24 24 26 27 28 29 30 31 36 37 39 40 41 41 42 48 48 48 2 2 80C186XL 80C188XL NOTE Pin names in parentheses applies to 80C188XL Figure 1 80C186XL 80C188XL Block Diagram 3 3 272431- 2 80C186XL 80C188XL (2a) 272431 - 3 272431 - 4 (2b) Note 1 XTAL Frequency L1 Value 20 MHz 12 0 mH g20% 25 MHz 8 2 mH g20% 32 MHz 4 7 mH g20% 40 MHz 3 0 mH g20% LC network is only required when using a third overtone crystal Figure 2 Oscillator Configurations (see text) INTRODUCTION Unless specifically noted all references to the 80C186XL apply to the 80C188XL References to pins that differ between the 80C186XL and the 80C188XL are given in parentheses The following Functional Description describes the base architecture of the 80C186XL The 80C186XL is a very high integration 16-bit microprocessor It combines 15-20 of the most common microprocessor system components onto one chip The 80C186XL is object code compatible with the 8086 8088 microprocessors and adds 10 new instruction types to the 8086 8088 instruction set The 80C186XL has two major modes of operation Compatible and Enhanced In Compatible Mode the 80C186XL is completely compatible with NMOS 80186 with the exception of 8087 support The Enhanced mode adds three new features to the system design These are Power-Save control Dynamic RAM refresh and an asynchronous Numerics Coprocessor interface (80C186XL only) The 80C186XL oscillator circuit is designed to be used either with a parallel resonant fundamental or third-overtone mode crystal depending upon the frequency range of the application This is used as the time base for the 80C186XL The output of the oscillator is not directly available outside the 80C186XL The recommended crystal configuration is shown in Figure 2b When used in third-overtone mode the tank circuit is recommended for stable operation Alternately the oscillator may be driven from an external source as shown in Figure 2a The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide by two counter This counter is used to drive all internal phase clocks and the external CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components All AC Timings are referenced to CLKOUT Intel recommends the following values for crystal selection parameters Temperature Range Application Specific ESR (Equivalent Series Resistance) 60X max 7 0 pF max C0 (Shunt Capacitance of Crystal) C1 (Load Capacitance) 20 pF g2 pF Drive Level 2 mW max 80C186XL CORE ARCHITECTURE 80C186XL Clock Generator The 80C186XL provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divideby-two counter synchronous and asynchronous ready inputs and reset circuitry 4 4 80C186XL 80C188XL spond to bus cycles An offset map of the 256-byte control register block is shown in Figure 3 Bus Interface Unit The 80C186XL provides a local bus controller to generate the local bus control signals In addition it employs a HOLD HLDA protocol for relinquishing the local bus to other bus masters It also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) information It is also responsible for reading data from the local bus during a read operation Synchronous and asynchronous ready input pins are provided to extend a bus cycle beyond the minimum four states (clocks) The 80C186XL bus controller also generates two control signals (DEN and DT R) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the multiplexed address data bus During RESET the local bus controller will perform the following action Chip-Select Ready Generation Logic The 80C186XL contains logic which provides programmable chip-select generation for both memories and peripherals In addition it can be programmed to provide READY (or WAIT state) generation It can also provide latched address bits A1 and A2 The chip-select lines are active for all memory and I O cycles in their programmed areas whether they be generated by the CPU or by the integrated DMA unit The 80C186XL provides 6 memory chip select outputs for 3 address areas upper memory lower memory and midrange memory One each is provided for upper memory and lower memory while four are provided for midrange memory OFFSET Relocation Register FEH DAH DMA Descriptors Channel 1 D0H Drive DEN RD and WR HIGH for one clock cycle then float them Drive S0-S2 to the inactive state (all HIGH) and then float CAH DMA Descriptors Channel 0 C0H Drive LOCK HIGH and then float Float AD0-15 (AD0-8) A16-19 (A9-A19) BHE (RFSH) DT R A8H Chip-Select Control Registers A0H Drive ALE LOW Drive HLDA LOW RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR and TEST BUSY pins have internal pullup devices which are active while RES is applied Excessive loading or grounding certain of these pins causes the 80C186XL to enter an alternative mode of operation 66H Time 2 Control Registers 60H 5EH Time 1 Control Registers 58H 56H Time 0 Control Registers 50H RD QSMD low results in Queue Status Mode UCS and LCS low results in ONCE Mode TEST BUSY low (and high later) results in Enhanced Mode 3EH Interrupt Controller Registers 20H 80C186XL PERIPHERAL ARCHITECTURE All the 80C186XL integrated peripherals are controlled by 16-bit registers contained within an internal 256-byte control block The control block may be mapped into either memory or I O space Internal logic will recognize control block addresses and re- Figure 3 Internal Register Map The 80C186XL provides a chip select called UCS for the top of memory The top of memory is usually used as the system memory because after reset the 80C186XL begins executing at memory location FFFF0H 5 5 80C186XL 80C188XL The 80C186XL provides a chip select for low memory called LCS The bottom of memory contains the interrupt vector table starting at location 00000H The 80C186XL provides four MCS lines which are active within a user-locatable memory block This block can be located within the 80C186XL 1 Mbyte memory address space exclusive of the areas defined by UCS and LCS Both the base address and size of this memory block are programmable The 80C186XL can generate chip selects for up to seven peripheral devices These chip selects are active for seven contiguous blocks of 128 bytes above a programmable base address The base address may be located in either memory or I O space The 80C186XL can generate a READY signal internally for each of the memory or peripheral CS lines The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0-3 wait states for all accesses to the area for which the chip select is active In addition the 80C186XL may be programmed to either ignore external READY for each chip-select range individually or to factor external READY with the integrated ready generator Upon RESET the Chip-Select Ready Logic will perform the following actions mum of 8 clocks) one cycle to fetch data and the other to store data Timer Counter Unit The 80C186XL provides three internal 16-bit programmable timers Two of these are highly flexible and are connected to four external pins (2 per timer) They can be used to count external events time external events generate nonrepetitive waveforms etc The third timer is not connected to any external pins and is useful for real-time coding and time delay applications In addition the third timer can be used as a prescaler to the other two or as a DMA request source Interrupt Control Unit The 80C186XL can receive interrupts from a number of sources both internal and external The 80C186XL has 5 external and 2 internal interrupt sources (Timer Couners and DMA) The internal interrupt controller serves to merge these requests on a priority basis for individual service by the CPU Enhanced Mode Operation In Compatible Mode the 80C186XL operates with all the features of the NMOS 80186 with the exception of 8087 support (i e no math coprocessing is possible in Compatible Mode) Queue-Status information is still available for design purposes other than 8087 support All the Enhanced Mode features are completely masked when in Compatible Mode A write to any of the Enhanced Mode registers will have no effect while a read will not return any valid data In Enhanced Mode the 80C186XL will operate with Power-Save DRAM refresh and numerics coprocessor support (80C186XL only) in addition to all the Compatible Mode features If connected to a math coprocessor (80C186XL only) this mode will be invoked automatically Without an NPX this mode can be entered by tying the RESET output signal from the 80C186XL to the TEST BUSY input All chip-select outputs will be driven HIGH Upon leaving RESET the UCS line will be programmed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert 3 wait states in conjunction with external READY (i e UMCS resets to FFFBH) No other chip select or READY control registers have any predefined values after RESET They will not become active until the CPU accesses their control registers DMA Unit The 80C186XL DMA controller provides two independent high-speed DMA channels Data transfers can occur between memory and I O spaces (e g Memory to I O) or within the same space (e g Memory to Memory or I O to I O) Data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses NOTE Only byte transfers are possible on the 80C188XL Each DMA channel maintains both a 20-bit source and destination pointer which can be optionally incremented or decremented after each data transfer (by one or two depending on byte or word transfers) Each data transfer consumes 2 bus cycles (a mini6 Queue-Status Mode The queue-status mode is entered by strapping the RD pin low RD is sampled at RESET and if LOW the 80C186XL will reconfigure the ALE and WR pins to be QS0 and QS1 respectively This mode is available on the 80C186XL in both Compatible and Enhanced Modes 6 80C186XL 80C188XL functions as in compatible mode and may be programmed for activity with ready logic and wait states accordingly As in Compatible Mode MCS2 will function for one-fourth a programmed block size Table 1 MCS Assignments Compatible Mode MCS0 MCS1 MCS2 MCS3 PEREQ ERROR MCS2 NPS Enhanced Mode Processor Extension Request NPX Error Mid-Range Chip Select Numeric Processor Select DRAM Refresh Control Unit The Refresh Control Unit (RCU) automatically generates DRAM refresh bus cycles The RCU operates only in Enhanced Mode After a programmable period of time the RCU generates a memory read request to the BIU If the address generated during a refresh bus cycle is within the range of a properly programmed chip select that chip select will be activated when the BIU executes the refresh bus cycle Power-Save Control The 80C186XL when in Enhanced Mode can enter a power saving state by internally dividing the processor clock frequency by a programmable factor This divided frequency is also available at the CLKOUT pin All internal logic including the Refresh Control Unit and the timers have their clocks slowed down by the division factor To maintain a real time count or a fixed DRAM refresh rate these peripherals must be re-programmed when entering and leaving the power-save mode ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80C186XL has a test mode available which allows all pins to be placed in a high-impedance state ONCE stands for ``ON Circuit Emulation'' When placed in this mode the 80C186XL will put all pins in the high-impedance state until RESET The ONCE mode is selected by tying the UCS and the LCS LOW during RESET These pins are sampled on the low-to-high transition of the RES pin The UCS and the LCS pins have weak internal pullup resistors similar to the RD and TEST BUSY pins to guarantee ONCE Mode is not entered inadvertently during normal operation LCS and UCS must be held low at least one clock after RES goes high to guarantee entrance into ONCE Mode Interface for 80C187 Math Coprocessor (80C186XL Only) In Enhanced Mode three of the mid-range memory chip selects are redefined according to Table 1 for use with the 80C187 The fourth chip select MCS2 7 7 80C186XL 80C188XL proper operation Stated simply missing a setup or hold on an asynchronous pin will result in something minor (i e a timer count will be missed) whereas missing a setup or hold on a synchronous pin result in system failure (the system will ``lock up'') An input pin may also be edge or level sensitive Column 4 Output States (for O and I O types only) The state of an output or I O pin is dependent on the operating mode of the device There are four modes of operation that are different from normal active mode Bus Hold Reset Idle Mode Powerdown Mode This column describes the output pin state in each of these modes The legend for interpreting the information in the Pin Descriptions is shown in Table 2 As an example please refer to the table entry for AD7 0 The ``I O'' signifies that the pins are bidirectional (i e have both an input and output function) The ``S'' indicates that as an input the signal must be synchronized to CLKOUT for proper operation The ``H(Z)'' indicates that these pins will float while the processor is in the Hold Acknowledge state R(Z) indicates that these pins will float while RESIN is low All pins float while the processor is in the ONCE Mode (with the exception of X2) PACKAGE INFORMATION This section describes the pin functions pinout and thermal characteristics for the 80C186XL in the Quad Flat Pack (QFP) Plastic Leaded Chip Carrier (PLCC) Leadless Chip Carrier (LCC) and the Shrink Quad Flat Pack (SQFP) For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide (Order Number 231369) Pin Descriptions Each pin or logical set of pins is described in Table 3 There are four columns for each entry in the Pin Description Table The following sections describe each column Column 1 Pin Name In this column is a mnemonic that describes the pin function Negation of the signal name (i e RESIN) implies that the signal is active low Column 2 Pin Type A pin may be either power (P) ground (G) input only (I) output only (O) or input output (I O) Please note that some pins have more than one function Column 3 Input Type (for I and I O types only) These are two different types of input pins on the 80C186XL asynchronous and synchronous Asynchronous pins require that setup and hold times be met only to guarantee recognition Synchronous input pins require that the setup and hold times be met to guarantee 8 8 80C186XL 80C188XL Table 2 Pin Description Nomenclature Symbol P G I O IO S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) Description Power Pin (apply a VCC voltage) Ground (connect to VSS) Input only pin Output only pin Input Output pin Synchronous edge sensitive Synchronous level sensitive Asynchronous edge sensitive Asynchronous level sensitive Output driven to VCC during bus hold Output driven to VSS during bus hold Output floats during bus hold Output remains active during bus hold Output retains current state during bus hold Output weakly held at VCC during reset Output driven to VCC during reset Output driven to VSS during reset Output floats during reset Output remains active during reset Output retains current state during reset 9 9 80C186XL 80C188XL Table 3 Pin Descriptions Pin Name VCC VSS RESET Pin Type P G O H(0) R(1) Input Type Output States System Ground RESET Output indicates that the CPU is being reset and can be used as a system reset It is active HIGH synchronized with the processor clock and lasts an integer number of clock periods corresponding to the length of the RES signal Reset goes inactive 2 clockout periods after RES goes inactive When tied to the TEST BUSY pin RESET forces the processor into enhanced mode RESET is not floated during bus hold Crystal Inputs X1 and X2 provide external connections for a fundamental mode or third overtone parallel resonant crystal for the internal oscillator X1 can connect to an external clock instead of a crystal In this case minimize the capacitance on X2 The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT) Clock Output provides the system with a 50% duty cycle waveform All device pin timings are specified relative to CLKOUT CLKOUT is active during reset and bus hold An active RES causes the processor to immediately terminate its present activity clear the internal logic and enter a dormant state This signal may be asynchronous to the clock The processor begins fetching instructions approximately 6 clock cycles after RES is returned HIGH For proper initialization VCC must be within specifications and the clock signal must be stable for more than 4 clocks with RES held LOW RES is internally synchronized This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network The TEST pin is sampled during and after reset to determine whether the processor is to enter Compatible or Enhanced Mode Enhanced Mode requires TEST to be HIGH on the rising edge of RES and LOW four CLKOUT cycles later Any other combination will place the processor in Compatible Mode During power-up active RES is required to configure TEST BUSY as an input A weak internal pullup ensures a HIGH state when the input is not externally driven TEST In Compatible Mode this pin is configured to operate as TEST This pin is examined by the WAIT instruction If the TEST input is HIGH when WAIT execution begins instruction execution will suspend TEST will be resampled every five clocks until it goes LOW at which time execution will resume If interrupts are enabled while the processor is waiting for TEST interrupts will be serviced BUSY (80C186XL Only) In Enhanced Mode this pin is configured to operate as BUSY The BUSY input is used to notify the 80C186XL of Math Coprocessor activity Floating point instructions executing in the 80C186XL sample the BUSY pin to determine when the Math Coprocessor is ready to accept a new command BUSY is active HIGH Pin Description System Power a 5 volt power supply X1 X2 I O A(E) H(Q) R(Q) CLKOUT O H(Q) R(Q) A(L) RES I TEST BUSY (TEST) I A(E) NOTE Pin names in parentheses apply to the 80C188XL 10 10 80C186XL 80C188XL Table 3 Pin Descriptions (Continued) Pin Name TMR IN 0 TMR IN 1 Pin Type I Input Type A(L) A(E) Output States Pin Description Timer Inputs are used either as clock or control signals depending upon the programmed timer mode These inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized Timer Inputs must be tied HIGH when not being used as clock or retrigger inputs H(Q) R(1) Timer outputs are used to provide single pulse or continuous waveform generation depending upon the timer mode selected These outputs are not floated during a bus hold DMA Request is asserted HIGH by an external device when it is ready for DMA Channel 0 or 1 to perform a transfer These signals are level-triggered and internally synchronized The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition from LOW to HIGH is latched and synchronized internally and initiates the interrupt at the next instruction boundary NMI must be asserted for at least one CLKOUT period The NonMaskable Interrupt cannot be avoided by programming Maskable Interrupt Requests can be requested by activating one of these pins When configured as inputs these pins are active HIGH Interrupt Requests are synchronized internally INT2 and INT3 may be configured to provide active-LOW interruptacknowledge output signals All interrupt inputs may be configured to be either edge- or level-triggered To ensure recognition all interrupt requests must remain active until the interrupt is acknowledged When Slave Mode is selected the function of these pins changes (see Interrupt Controller section of this data sheet) Address Bus Outputs and Bus Cycle Status (3 - 6) indicate the four most significant address bits during T1 These signals are active HIGH During T2 T3 TW and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a DMAinitiated or refresh bus cycle During the same T-states S3 S4 and S5 are always LOW On the 80C188XL A15 - A8 provide valid address information for the entire bus cycle IO S(L) H(Z) R(Z) Address Data Bus signals constitute the time multiplexed memory or I O address (T1) and data (T2 T3 TW and T4) bus The bus is active HIGH For the 80C186XL A0 is analogous to BHE for the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is to be transferred onto the lower portion of the bus in memory or I O operations TMR OUT 0 TMR OUT 1 O DRQ0 DRQ1 I A(L) NMI I A(E) INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 IRQ I IO A(E) A(L) A(E) A(L) H(1) R(Z) A19 S6 A18 S5 A17 S4 A16 S3 (A8-A15) O H(Z) R(Z) AD0-AD15 (AD0-AD7) NOTE Pin names in parentheses apply to the 80C188XL 11 11 80C186XL 80C188XL Table 3 Pin Descriptions (Continued) Pin Name BHE (RFSH) Pin Type O Input Type Output States H(Z) R(Z) Pin Description The BHE (Bus High Enable) signal is analogous to A0 in that it is used to enable data on to the most significant half of the data bus pins D15 - D8 BHE will be LOW during T1 when the upper byte is transferred and will remain LOW through T3 and TW BHE does not need to be latched On the 80C188XL RFSH is asserted LOW to indicate a refresh bus cycle In Enhanced Mode BHE (RFSH) will also be used to signify DRAM refresh cycles A refresh cycle is indicated by both BHE (RFSH) and A0 being HIGH 80C186XL BHE and A0 Encodings BHE Value 0 0 1 1 ALE QS0 O H(0) R(0) H(Z) R(Z) A0 Value 0 1 0 1 Function Word Transfer Byte Transfer on upper half of data bus (D15 - D8) Byte Transfer on lower half of data bus (D7 -D0) Refresh Address Latch Enable Queue Status 0 is provided by the processor to latch the address ALE is active HIGH with addresses guaranteed valid on the trailing edge Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a memory or an I O device It is active LOW When the processor is in Queue Status Mode the ALE QS0 and WR QS1 pins provide information about processor instruction queue interaction QS1 0 0 1 1 QS0 0 1 1 0 Queue Operation No queue operation First opcode byte fetched from the queue Subsequent byte fetched from the queue Empty the queue WR QS1 O RD QSMD O H(Z) R(1) Read Strobe is an active LOW signal which indicates that the processor is performing a memory or I O read cycle It is guaranteed not to go LOW before the A D bus is floated An internal pull-up ensures that RD QSMD is HIGH during RESET Following RESET the pin is sampled to determine whether the processor is to provide ALE RD and WR or queue status information To enable Queue Status Mode RD must be connected to GND Asynchronous Ready informs the processor that the addressed memory space or I O device will complete a data transfer The ARDY pin accepts a rising edge that is asynchronous to CLKOUT and is active HIGH The falling edge of ARDY must be synchronized to the processor clock Connecting ARDY HIGH will always assert the ready condition to the CPU If this line is unused it should be tied LOW to yield control to the SRDY pin ARDY I A(L) S(L) NOTE Pin names in parentheses apply to the 80C188XL 12 12 80C186XL 80C188XL Table 3 Pin Descriptions (Continued) Pin Name SRDY Pin Type I Input Type S(L) Output States Pin Description Synchronous Ready informs the processor that the addressed memory space or I O device will complete a data transfer The SRDY pin accepts an active-HIGH input synchronized to CLKOUT The use of SRDY allows a relaxed system timing over ARDY This is accomplished by elimination of the one-half clock cycle required to internally synchonize the ARDY input signal Connecting SRDY high will always assert the ready condition to the CPU If this line is unused it should be tied LOW to yield control to the ARDY pin H(Z) R(Z) LOCK output indicates that other system bus masters are not to gain control of the system bus LOCK is active LOW The LOCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction immediately following the LOCK prefix It remains active until the completion of that instruction No instruction prefetching will occur while LOCK is asserted Bus cycle status S0 -S2 are encoded to provide bus-transaction information Bus Cycle Status Information S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Read I O Write I O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (no bus cycle) LOCK O S0 S1 S2 O H(Z) R(1) S2 may be used as a logical M IO indicator and S1 as a DT R indicator HOLD HLDA I O A(L) H(1) R(0) HOLD indicates that another bus master is requesting the local bus The HOLD input is active HIGH The processor generates HLDA (HIGH) in response to a HOLD request Simultaneous with the issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor will lower HLDA When the processor needs to run another bus cycle it will again drive the local bus and control lines In Enhanced Mode HLDA will go low when a DRAM refresh cycle is pending in the processor and an external bus master has control of the bus It will be up to the external master to relinquish the bus by lowering HOLD so that the processor may execute the refresh cycle NOTE Pin names in parentheses apply to the 80C188XL 13 13 80C186XL 80C188XL Table 3 Pin Descriptions (Continued) Pin Name UCS Pin Type IO Input Type A(L) Output States H(1) R(WH) Pin Description Upper Memory Chip Select is an active LOW output whenever a memory reference is made to the defined upper portion (1K - 256K block) of memory The address range activating UCS is software programmable UCS and LCS are sampled upon the rising edge of RES If both pins are held low the processor will enter ONCE Mode In ONCE Mode all pins assume a high impedance state and remain so until a subsequent RESET UCS has a weak internal pullup that is active during RESET to ensure that the processor does not enter ONCE Mode inadvertently Lower Memory Chip Select is active LOW whenever a memory reference is made to the defined lower portion (1K - 256K) of memory The address range activating LCS is software programmable UCS and LCS are sampled upon the rising edge of RES If both pins are held low the processor will enter ONCE Mode In ONCE Mode all pins assume a high impedance state and remain so until a subsequent RESET LCS has a weak internal pullup that is active only during RESET to ensure that the processor does not enter ONCE mode inadvertently Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the defined midrange portion of memory (8K - 512K) The address ranges activating MCS0 - 3 are software programmable On the 80C186XL in Enhanced Mode MCS0 becomes a PEREQ input (Processor Extension Request) When connected to the Math Coprocessor this input is used to signal the 80C186XL when to make numeric data transfers to and from the coprocessor MCS3 becomes NPS (Numeric Processor Select) which may only be activated by communication to the 80C187 MCS1 becomes ERROR in Enhanced Mode and is used to signal numerics coprocessor errors Peripheral Chip Select signals 0 - 4 are active LOW when a reference is made to the defined peripheral area (64 Kbyte I O or 1 MByte memory space) The address ranges activating PCS0 - 4 are software programmable Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth peripheral chip select or to provide an internally latched A1 signal The address range activating PCS5 is software-programmable PCS5 A1 does not float during bus HOLD When programmed to provide latched A1 this pin will retain the previously latched value during HOLD LCS IO A(L) H(1) R(WH) MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS IO O A(L) H(1) R(WH) H(1) R(1) PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 O H(1) R(1) O H(1) H(X) R(1) NOTE Pin names in parentheses apply to the 80C188XL 14 14 80C186XL 80C188XL Table 3 Pin Descriptions (Continued) Pin Name PCS6 A2 Pin Type O Input Type Output States H(1) H(X) R(1) Pin Description Peripheral Chip Select 6 or Latched A2 may be programmed to provide a seventh peripheral chip select or to provide an internally latched A2 signal The address range activating PCS6 is software-programmable PCS6 A2 does not float during bus HOLD When programmed to provide latched A2 this pin will retain the previously latched value during HOLD Data Transmit Receive controls the direction of data flow through an external data bus transceiver When LOW data is transferred to the procesor When HIGH the processor places write data on the data bus Data Enable is provided as a data bus transceiver output enable DEN is active LOW during each memory and I O access (including 80C187 access) DEN is HIGH whenever DT R changes state During RESET DEN is driven HIGH for one clock then floated Not connected To maintain compatibility with future products do not connect to these pins DT R O H(Z) R(Z) DEN O H(Z) R(1 Z) NC NOTE Pin names in parentheses apply to the 80C188XL 15 15 80C186XL 80C188XL Ceramic Leadless Chip Carrier (JEDEC Type A) Contacts Facing Up Contacts Facing Down 272431 - 5 Ceramic Pin Grid Array Pins Facing Up Pins Facing Down 272431 - 6 NOTE XXXXXXXXC indicates the Intel FPO number Figure 4 80C186XL 80C188XL Pinout Diagrams 16 16 80C186XL 80C188XL Shrink Quad Flat Pack 272431 - 22 NOTE XXXXXXXXC indicates the Intel FPO number Figure 4 80C186XL 80C188XL Pinout Diagrams (Continued) 17 17 80C186XL 80C188XL Plastic Leaded Chip Carrier Contacts Facing Up Contacts Facing Down 272431 - 7 80-Pin Quad Flat Pack (EIAJ) Contacts Facing Up Contacts Facing Down 272431 - 8 NOTE XXXXXXXXA indicates the Intel FPO number Figure 4 80C186XL 80C288XL Pinout Diagrams (Continued) 18 18 80C186XL 80C188XL Table 4 LCC PLCC Pin Functions with Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 S3 A17 S4 A18 S5 A19 S6 17 15 13 11 8 6 4 2 16 14 12 10 7 5 3 1 68 67 66 65 Bus Control ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DEN DT R LOCK HOLD HLDA 61 64 52 53 54 62 63 55 49 39 40 48 50 51 Processor Control RES RESET X1 X2 CLKOUT TEST BUSY NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 24 57 59 58 56 47 46 45 44 42 41 UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 DRQ0 DRQ1 NOTE Pin names in parentheses apply to the 80C188XL IO 34 33 38 37 36 35 25 27 28 29 30 31 32 20 21 22 23 18 19 Power and Ground VCC VCC VSS VSS 9 43 26 60 Table 5 LCC PGA PLCC Pin Locations with Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AD15 (A15) AD7 AD14 (A14) AD6 AD13 (A13) AD5 AD12 (A12) AD4 VCC AD11 (A11) AD3 AD10 (A10) AD2 AD9 (A9) AD1 AD8 (A8) AD0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DRQ0 DRQ1 TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 RES PCS0 VSS PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 LCS UCS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 MCS3 NPS MCS2 MCS1 ERROR MCS0 PEREQ DEN DT R INT3 INTA1 INT2 INTA0 VCC INT1 SELECT INT0 NMI TEST BUSY LOCK SRDY HOLD HLDA 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 S0 S1 S2 ARDY CLKOUT RESET X2 X1 VSS ALE QS0 RD QSMD WR QS1 BHE (RFSH) A19 S2 A18 S3 A17 S4 A16 S3 NOTE Pin names in parentheses apply to the 80C188XL 19 19 80C186XL 80C188XL Table 6 QFP Pin Functions with Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 S3 A17 S4 A18 S5 A19 S6 64 66 68 70 74 76 78 80 65 67 69 71 75 77 79 1 3 4 5 6 Bus Control ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DEN DT R LOCK HOLD HLDA No Connection NC NC NC NC NC NC NC NC NC 2 11 14 15 24 43 44 62 63 10 7 23 22 21 9 8 20 27 38 37 28 26 25 Processor Control RES RESET X1 X2 CLKOUT TEST BUSY NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 55 18 16 17 19 29 30 31 32 35 36 UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 DRQ0 DRQ1 IO 45 46 39 40 41 42 54 52 51 50 49 48 47 59 58 57 56 61 60 Power and Ground VCC VCC VCC VCC VSS VSS VSS 33 34 72 73 12 13 53 NOTE Pin names in parentheses apply to the 80C188XL Table 7 QFP Pin Locations with Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD15 (A15) NC A16 S3 A17 S4 A18 S5 A19 S6 BHE (RFSH) WR QS1 RD QSMD ALE QS0 NC VSS VSS NC NC X1 X2 RESET CLKOUT ARDY 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S2 S1 S0 NC HLDA HOLD SRDY LOCK TEST BUSY NMI INT0 INT1 SELECT VCC VCC INT2 INTA0 INT3 INTA1 DT R DEN MCS0 PEREQ MCS1 ERROR 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 MCS2 MCS3 NPS NC NC UCS LCS PCS6 A2 PCS5 A1 PCS4 PCS3 PCS2 PCS1 VSS PCS0 RES TMR OUT 1 TMR OUT 0 TMR IN 1 TMR IN 0 DRQ1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DRQ0 NC NC AD0 AD8 (A8) AD1 AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) VCC VCC AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 NOTE Pin names in parentheses apply to the 80C188XL 20 20 80C186XL 80C188XL Table 8 SQFP Pin Functions with Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 S3 A17 S4 A18 S5 A19 S6 1 3 6 8 12 14 16 18 2 5 7 9 13 15 17 19 21 22 23 24 Bus Control ALE QS0 BHE (RFSH) S0 S1 S2 RD QSMD WR QS1 ARDY SRDY DEN DT R LOCK HOLD HLDA No Connection NC NC NC NC NC 4 25 35 55 72 29 26 40 39 38 28 27 37 44 56 54 45 43 42 Processor Control RES RESET X1 X2 CLKOUT TEST BUSY NMI INT0 INT1 SELECT INT2 INTA0 INT3 INTA1 73 34 32 33 36 46 47 48 49 52 53 UCS LCS MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 A1 PCS6 A2 TMR IN 0 TMR IN 1 TMR OUT 0 TMR OUT 1 DRQ0 DRQ1 IO 62 63 57 58 59 60 71 69 68 67 66 65 64 77 76 75 74 79 78 Power and Ground VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS 10 11 20 50 51 61 30 31 41 70 80 NOTE Pin names in parentheses apply to the 80C188XL Table 9 SQFP Pin Locations with Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD0 AD8 (A8) AD1 NC AD9 (A9) AD2 AD10 (A10) AD3 AD11 (A11) VCC VCC AD4 AD12 (A12) AD5 AD13 (A13) AD6 AD14 (A14) AD7 AD15 (A15) VCC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A16 S3 A17 S4 A18 S5 A19 S6 NC BHE (RFSH) WR QS1 RD QSMD ALE QS0 VSS VSS X1 X2 RESET NC CLKOUT ARDY S2 S1 S0 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS HLDA HOLD SRDY LOCK TEST BUSY NMI INT0 INT1 SELECT VCC VCC INT2 INTA0 INT3 INTA1 DT R NC DEN MCS0 PEREQ MCS1 ERROR MCS2 MCS3 NPS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCC UCS LCS PCS6 A2 PCS5 A1 PCS4 PCS3 PCS2 PCS1 VSS PCS0 NC RES TMR OUT 1 TMR OUT 0 TMR IN 1 TMR IN 0 DRQ1 DRQ0 VSS NOTE Pin names in parentheses apply to the 80C188XL 21 21 80C186XL 80C188XL ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ambient Temperature under Bias Storage Temperature Voltage on Any Pin with Respect to Ground 0 C to a 70 C b 65 C to a 150 C b 1 0V to a 7 0V NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design Package Power Dissipation 1W Not to exceed the maximum allowable die temperature based on thermal resistance of the package WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability NOTICE The specifications are subject to change without notice DC SPECIFICATIONS Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH ICC Parameter Input Low Voltage (Except X1) Clock Input Low Voltage (X1) TA e 0 C to a 70 C VCC e 5V g10% Min b0 5 b0 5 Max 0 2 VCC b 0 3 06 VCC a 0 5 VCC a 0 5 VCC a 0 5 0 45 Units V V V V V V V V mA mA mA mA mA mA V Test Conditions Input High Voltage (All except X1 and RES) Input High Voltage (RES) Clock Input High Voltage (X1) Output Low Voltage Output High Voltage 0 2 VCC a 0 9 30 39 IOL e 2 5 mA (S0 1 2) IOL e 2 0 mA (others) IOH e b 2 4 mA IOH e b 200 mA 25 MHz 0 C VCC e 5 5V(3) 20 MHz 0 C VCC e 5 5V(3) 12 MHz 0 C VCC e 5 5V (3) DC 0 C VCC e 5 5V 0 5 MHz 0 45V s VIN s VCC 0 5 MHz 0 45V s VOUT s VCC(1) ICLO e 4 0 mA 2 4V (4) VCC b 0 5(4) 24 VCC b 0 5 VCC VCC 100 90 62 5 100 Power Supply Current ILI ILO VCLO Input Leakage Current Output Leakage Current Clock Output Low g10 g10 0 45 22 22 80C186XL 80C188XL DC SPECIFICATIONS (Continued) TA e 0 C to a 70 C Symbol VCHO CIN CIO Parameter Clock Output High Input Capacitance Output or I O Capacitance Min VCC b 0 5 VCC e 5V g10% Max Units V 10 20 pF pF Test Conditions ICHO e b 500 mA 1 MHz(2) 1 MHz(2) NOTES 1 Pins being floated during HOLD or by invoking the ONCE Mode 2 Characterization conditions are a) Frequency e 1 MHz b) Unmeasured pins at GND c) VIN at a 5 0V or 0 45V This parameter is not tested 3 Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open 4 RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR and TEST BUSY pins have internal pullup devices Loading some of these pins above IOH e b200 mA can cause the processor to go into alternative modes of operation See the section on Local Bus Controller and Reset for details Power Supply Current Current is linearly proportional to clock frequency and is measured with the device in RESET with X1 and X2 driven and all other non-power pins open Maximum current is given by ICC e 5 mA c freq (MHz) a IQL IQL is the quiescent leakage current when the clock is static IQL is typically less than 100 mA 272431 - 9 Figure 5 ICC vs Frequency 23 23 80C186XL 80C188XL AC SPECIFICATIONS MAJOR CYCLE TIMINGS (READ CYCLE) TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TDVCL TCLDX TCHSV TCLSH TCLAV TCLAX TCLDV TCHLH TLHLL TCHLL TAVLL TLLAX TAVCH TCLAZ Data in Setup (A D) Data in Hold (A D) 8 3 10 3 15 3 ns ns 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Data Valid Delay 3 3 3 0 3 10 20 TCLCL b 15 20 TCLCH b 10 TCHCL b 8 0 TCLAX 3 TCLCH b 10 3 0 3 3 3 3 17 17 20 17 17 20 20 TCLCH b 10 TCHCL b 10 0 TCLAX 3 TCLCH b 10 3 0 3 3 3 3 22 22 22 22 20 20 25 TCLCL b 15 20 TCLCH b 15 TCHCL b 15 0 TCLAX 3 TCLCH b 10 3 0 3 3 3 3 37 37 37 37 30 25 33 20 20 20 20 3 3 3 0 3 10 20 TCLCL b 15 25 27 25 25 27 3 3 3 0 3 10 25 36 35 35 36 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading Equal Loading Equal Loading Equal Loading TCHDX Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Address Valid to ALE Low Address Hold from ALE Inactive Address Valid to Clock High Address Float Delay TCLCSV Chip-Select Active Delay TCXCSX Chip-Select Hold from Command Inactive TCHCSX Chip-Select Inactive Delay TDXDL DEN Inactive to DT R Low TCVCTV Control Active Delay 1 TCVDEX DEN Inactive Delay TCHCTV Control Active Delay 2 TCLLV LOCK Valid Invalid Delay 24 24 80C186XL 80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (READ CYCLE) (Continued) TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL TIMING RESPONSES (Read Cycle) TAZRL TCLRL TRLRH TCLRH TRHLH TRHAV Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High RD Inactive to Address Active 0 3 2TCLCL b 15 3 TCLCH b 14 TCLCL b 15 20 20 0 3 2TCLCL b 20 3 TCLCH b 14 TCLCL b 15 27 27 0 3 2TCLCL b 25 3 TCLCH b 14 TCLCL b 15 37 37 ns ns ns ns ns ns Equal Loading Equal Loading 25 25 80C186XL 80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (WRITE CYCLE) TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) TCHSV TCLSH TCLAV TCLAX TCLDV TCHDX TCHLH TLHLL TCHLL TAVLL TLLAX TAVCH Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Address Valid to ALE Low Address Hold from ALE Inactive Address Valid to Clock High TCLCH b 10 TCHCL b 10 0 3 3 3 3 TCLCH b 10 3 0 3 17 17 20 17 20 TCLCL b 15 20 TCLCH b 10 TCHCL b 10 0 3 3 3 3 TCLCH b 10 3 0 3 22 20 25 25 25 3 3 3 0 3 10 20 TCLCL b 15 20 TCLCH b 15 TCHCL b 15 0 3 3 3 3 TCLCH b 10 3 0 3 37 30 37 37 33 20 20 20 20 3 3 3 0 3 10 20 TCLCL b 15 25 27 25 25 27 3 3 3 0 3 10 25 36 35 35 36 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading Equal Loading Equal Loading Equal Loading TCLDOX Data Hold Time TCVCTV Control Active Delay 1 TCVCTX Control Inactive Delay TCLCSV Chip-Select Active Delay TCXCSX Chip-Select Hold from Command Inactive TCHCSX Chip-Select Inactive Delay TDXDL TCLLV DEN Inactive to DT R Low LOCK Valid Invalid Delay 80C186XL TIMING RESPONSES (Write Cycle) TWLWH WR Pulse Width TWHLH WR Inactive to ALE High TWHDX Data Hold after WR 2TCLCL b 15 TCLCH b 14 TCLCL b 10 2TCLCL b 20 TCLCH b 14 TCLCL b 15 TCLCH b 10 2TCLCL b 25 TCLCH b 14 TCLCL b 20 TCLCH b 10 ns ns ns ns Equal Loading Equal Loading Equal Loading TWHDEX WR Inactive to DEN Inactive TCLCH b 10 26 26 80C186XL 80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE) TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TDVCL TCLDX TCHSV TCLSH TCLAV TAVCH TCLAX TCLDV TCHLH TLHLL TCHLL TAVLL TLLAX TCLAZ Data in Setup (A D) Data in Hold (A D) 8 3 10 3 15 3 ns ns 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) Status Active Delay Status Inactive Delay Address Valid Delay Address Valid to Clock High Address Hold Data Valid Delay 3 3 3 0 0 3 10 20 TCLCL b 15 20 TCLCH b 10 TCHCL b 10 TCLAX 3 3 0 3 3 3 20 17 17 20 17 17 TCLCH b 10 TCHCL b 10 TCLAX 3 3 0 3 3 3 22 22 22 20 25 25 TCLCL b 15 20 TCLCH b 15 TCHCL b 15 TCLAX 3 3 0 3 3 3 37 37 37 25 37 37 20 20 20 20 3 3 3 0 0 3 10 20 TCLCL b 15 25 27 25 25 27 3 3 3 0 0 3 10 25 36 35 35 36 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading Equal Loading Equal Loading TCHDX Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Address Valid to ALE Low Address Hold to ALE Inactive Address Float Delay TCVCTV Control Active Delay 1 TCVCTX Control Inactive Delay TDXDL DEN Inactive to DT R Low TCHCTV Control Active Delay 2 TCVDEX DEN Inactive Delay (Non-Write Cycles) TCLLV LOCK Valid Invalid Delay 27 27 80C186XL 80C188XL AC SPECIFICATIONS (Continued) SOFTWARE HALT CYCLE TIMINGS TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) TCHSV TCLSH TCLAV TCHLH TLHLL TCHLL TDXDL Status Active Delay Status Inactive Delay Address Valid Delay ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT R Low 3 TCLCL b 15 20 0 20 3 3 3 3 20 20 20 20 TCLCL b 15 20 0 22 3 3 3 3 25 25 27 20 TCLCL b 15 25 0 37 3 3 3 35 35 36 25 ns ns ns ns ns ns ns ns Equal Loading TCHCTV Control Active Delay 2 28 28 80C186XL 80C188XL AC SPECIFICATIONS (Continued) CLOCK TIMINGS TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min 80C186XL CLKIN REQUIREMENTS(1) TCKIN TCLCK TCHCK TCKHL TCKLH TCICO TCLCL TCLCH TCHCL CLKIN Period CLKIN Low Time CLKIN High Time CLKIN Fall Time CLKIN Rise Time 20 8 8 % % % 5 5 25 10 10 % % % 5 5 40 16 16 % % % 5 5 ns ns 1 5V(2) ns 1 5V(2) ns 3 5 to 1 0V ns 1 0 to 3 5V Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL CLKOUT TIMING CLKIN to CLKOUT Skew CLKOUT Period CLKOUT Low Time CLKOUT High Time 40 0 5 TCLCL b 5 0 5 TCLCL b 5 6 6 17 % 50 0 5 TCLCL b 5 0 5 TCLCL b 5 8 8 17 80 0 5 TCLCL b 5 0 5 TCLCL b 5 10 10 21 % ns ns ns CL e 100 pF(3) ns CL e 100 pF(4) ns 1 0 to 3 5V ns 3 5 to 1 0V TCH1CH2 CLKOUT Rise Time TCL2CL1 CLKOUT Fall Time NOTES 1 External clock applied to X1 and X2 not connected 2 TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 40% of TCKIN 3 Tested under worst case conditions VCC e 5 5V TA e 70 C 4 Tested under worst case conditions VCC e 4 5V TA e 0 C 29 29 80C186XL 80C188XL AC SPECIFICATIONS (Continued) READY PERIPHERAL AND QUEUE STATUS TIMINGS TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Unit Min Max Test Conditions 80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once) TSRYCL TCLSRY TARYCH TCLARX Synchronous Ready (SRDY) Transition Setup Time(1) SRDY Transition Hold Time(1) ARDY Resolution Transition Setup Time(2) ARDY Active Hold Time(1) 8 8 8 8 8 10 8 8 10 10 10 10 10 15 10 10 15 15 15 15 15 25 15 15 ns ns ns ns ns ns ns ns TARYCHL ARDY Inactive Holding Time TARYLCL Asynchronous Ready (ARDY) Setup Time(1) TINVCH TINVCL TCLTMV TCHQSV INTx NMI TEST BUSY TMR IN Setup Time(2) DRQ0 DRQ1 Setup Time(2) 80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES Timer Output Delay Queue Status Delay 17 22 22 27 33 32 ns ns NOTES 1 To guarantee proper operation 2 To guarantee recognition at clock edge 30 30 80C186XL 80C188XL AC SPECIFICATIONS (Continued) RESET AND HOLD HLDA TIMINGS TA e 0 C to a 70 C VCC e 5V g10% All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted All output test conditions are with CL e 50 pF For AC tests input VIL e 0 45V and VIH e 2 4V except at X1 where VIH e VCC b 0 5V Values Symbol Parameter 80C186XL25 Min Max 80C186XL20 Min Max 80C186XL12 Min Max Unit Test Conditions 80C186XL RESET AND HOLD HLDA TIMING REQUIREMENTS TRESIN THVCL TCLAZ TCLAV TCLRO TCLHAV TCHCZ TCHCV RES Setup HOLD Setup(1) 15 8 15 10 15 15 ns ns 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) Address Float Delay Address Valid Delay TCLAX 3 20 20 TCLAX 3 20 22 TCLAX 3 25 36 ns ns 80C186XL RESET AND HOLD HLDA TIMING RESPONSES Reset Delay HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) 3 17 17 22 20 3 22 22 25 26 3 33 33 33 36 ns ns ns ns NOTE 1 To guarantee recognition at next clock 31 31 80C186XL 80C188XL AC SPECIFICATIONS (Continued) 272431 - 10 NOTES 1 Status inactive in state preceding T4 2 If latched A1 and A2 are selected instead of PCS5 and PCS6 only TCLCSV is applicable 3 For write cycle followed by read cycle 4 T1 of next bus cycle 5 Changes in T-state preceding next bus cycle if followed by write Pin names in parentheses apply to the 80C188XL Figure 6 Read Cycle Waveforms 32 32 80C186XL 80C188XL AC SPECIFICATIONS (Continued) 272431 - 11 NOTES 1 Status inactive in state preceding T4 2 If latched A1 and A2 are selected instead of PCS5 and PCS6 only TCLCSV is applicable 3 For write cycle followed by read cycle 4 T1 of next bus cycle 5 Changes in T-state preceding next bus cycle if followed by read INTA or halt Pin names in parentheses apply to the 80C188XL Figure 7 Write Cycle Waveforms 33 33 80C186XL 80C188XL AC SPECIFICATIONS (Continued) 272431 - 12 NOTES 1 Status inactive in state preceding T4 2 The data hold time lasts only until INTA goes inactive even if the INTA transition occurs prior to TCLDX (min) 3 INTA occurs one clock later in Slave Mode 4 For write cycle followed by interrupt acknowledge cycle 5 LOCK is active upon T1 of the first interrupt acknowledge cycle and inactive upon T2 of the second interrupt acknowledge cycle 6 Changes in T-state preceding next bus cycle if followed by write Pin names in parentheses apply to the 80C188XL Figure 8 Interrupt Acknowledge Cycle Waveforms 34 34 80C186XL 80C188XL AC SPECIFICATIONS (Continued) 272431 - 13 NOTE 1 For write cycle followed by halt cycle Pin names in parentheses apply to the 80C188XL Figure 9 Software Halt Cycle Waveforms 35 35 80C186XL 80C188XL WAVEFORMS 272431 - 14 Figure 10 Clock Waveforms 272431 - 15 Figure 11 Reset Waveforms 272431 - 16 Figure 12 Synchronous Ready (SRDY) Waveforms 36 36 80C186XL 80C188XL AC CHARACTERISTICS 272431 - 23 Figure 13 Asynchronous Ready (ARDY) Waveforms 272431 - 17 Figure 14 Peripheral and Queue Status Waveforms 37 37 80C186XL 80C188XL AC CHARACTERISTICS (Continued) 272431 - 24 Figure 15 HOLDA HLDA Waveforms (Entering Hold) 272431 - 18 Figure 16 HOLD HLDA Waveforms (Leaving Hold) 38 38 80C186XL 80C188XL EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters The first character is always a `T' (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address ARY Asynchronous Ready Input C CK CS CT D DE H Clock Output Clock Input Chip Select Control (DT R DEN Data Input DEN Logic Level High ) OUT Input (DRQ0 TIM0 ) L Logic Level Low or ALE O QS R S V W X Z Output Queue Status (QS1 QS2) RD Signal RESET Signal Status (S0 S1 S2) Valid WR Signal No Longer a Valid Logic Level Float SRY Synchronous Ready Input Examples TCLAV Time from Clock low to Address valid TCHLH Time from Clock high to ALE high Time from Clock low to Chip Select valid TCLCSV 39 39 80C186XL 80C188XL DERATING CURVES Typical Output Delay Capacitive Derating 272431 - 19 Figure 17 Capacitive Derating Curve Typical Rise and Fall Times for TTL Voltage Levels 272431 - 20 Figure 18 TTL Level Rise and Fall Times for Output Buffers Typical Rise and Fall Times for CMOS Voltage Levels 272431 - 21 Figure 19 CMOS Level Rise and Fall Times for Output Buffers 40 40 80C186XL 80C188XL 80C186XL 80C188XL EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the 80C186XL microprocessor EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards The 80C186XL EXPRESS program includes an extended temperature range With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to a 70 C With the extended temperature range option operational characteristics are guaranteed over the range of b 40 C to a 85 C Package types and EXPRESS versions are identified by a one or two-letter prefix to the part number The prefixes are listed in Table 10 All AC and DC specifications not mentioned in this section are the same for both commercial and EXPRESS parts Table 10 Prefix Identification Prefix A N R S SB TA TN TR TS Package Type PGA PLCC LCC QFP SQFP PGA PLCC LCC QFP Temperature Range Commercial Commercial Commercial Commercial Commercial Extended Extended Extended Extended 80C186XL 80C188XL EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address boundaries (80C186XL only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit With a 16-bit BIU the 80C186XL has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program execution time will not be substantially greater than that derived from adding the instruction timings shown The 80C188XL 8-bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown 41 41 80C186XL 80C188XL INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 9 7 15 6 26 26 2 3 13 12 1110010w 1110110w port 10 8 10 8 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 24 14 12 83 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 20 14 13 14 68 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12 13 34 8 9 29 2 11 2 12 29 12 13 34 8 9 2 13 2 15 8 16-bit 8 16-bit Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 42 42 80C186XL 80C188XL INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26-28 35-37 32-34 41-43 26-28 35-37 32-34 41-43 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 2 2 2 2 Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 43 43 80C186XL 80C188XL INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit count 2 15 2 15 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44-52 53-61 50-58 59-67 19 15 2 4 44-52 53-61 50-58 59-67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25-28 34-37 31-34 40-43 22-25 29-32 25-28 34-37 32-34 40-43 22-25 29-32 Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 29 38 35 44 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 44 44 80C186XL 80C188XL INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 3 10 4 16 34 3 10 8 16-bit Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 19 17 27 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 31 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 54 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 14 14 11 21 11101010 segment offset segment selector 14 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 45 45 80C186XL 80C188XL INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 25 22 a 16(n b 1) 8 19 29 26 a 20(n b 1) 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33-35 28 33-35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 46 46 80C186XL 80C188XL INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix NOP e No Operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 10010000 (TTT LLL are opcode to processor extension) 2 2 2 2 2 2 2 2 6 2 3 2 2 2 2 2 2 2 2 6 2 3 if TEST e 0 Format 80C186XL Clock Cycles 80C188XL Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disphigh are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP if r m DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following Segment Register ES CS SS DS reg 00 01 10 11 REG is assigned according to the following table 16-Bit (w e 1) 8-Bit (w e 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 47 47 80C186XL 80C188XL 1 An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1 This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists This errata will not occur consistently it is dependent on interrupt timing The C step 80C186XL 80C188XL has no known errata The C step can be identified by the presence of a ``C'' or ``D'' alpha character next to the FPO number The FPO number location is shown in Figure 4 REVISION HISTORY This data sheet 272031-002 270975-002 272309-001 272310-001 replaces the following data sheets 80C186XL 80C188XL SB80C186XL SB80C188XL ERRATA An A or B step 80C186XL 80C188XL has the following errata The A or B step 80C186XL 80C188XL can be identified by the presence of an ``A'' or ``B'' alpha character respectively next to the FPO number The FPO number location is shown in Figure 4 PRODUCT IDENTIFICATION Intel 80C186XL devices are marked with a 9-character alphanumeric Intel FPO number underneath the product number This data sheet (272431-001) is valid for devices with an ``A'' ``B'' ``C'' or ``D'' as the ninth character in the FPO number as illustrated in Figure 4 48 48 |
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